1. Field
Embodiments of the invention relate to the field of system testing and more specifically, but not exclusively, to combinatorial at-speed scan testing.
2. Background Information
Automatic test pattern generation (ATPG) systems use tools for testing digital circuits after the circuits have been manufactured. In general, an ATPG tool generates a set of test vectors that are applied to a circuit under test. The output of the circuit is analyzed to identify logic faults in the circuit design (a.k.a. “functional testing”) as well as detecting fabrication defects (a.k.a., “structural testing”).
At-speed testing refers to testing techniques to detect defects that are only apparent when the circuit is running at system speed. Many time-based defects cannot be detected unless the circuit is run at-speed. Time related defects that occur at-speed include high impedance shorts, in-line resistance, and cross talk between signals.
Two fault models used in at-speed testing are path-delay fault modeling and transition fault modeling. In general, fault modeling is the translation of physical defects in the circuit to a mathematical construct that can be understood and manipulated by testing software. Path-delay fault modeling tests the combined delay through a predetermined set of logic gates. Transition fault modeling models a gross delay at every logic gate terminal. Transition faults include slow-to-rise and slow-to-fall delays at a gate terminal.
At-speed scan testing for path-delay fault modeling and transition fault modeling involve similar procedures. In general, a test pattern is loaded into a scan chain. The test pattern is launched into the circuit under test and the results captured by a single or a pair of at-speed clock pulses. And then the results of the test pattern are shifted out of the scan chain.
Two types of transition fault modeling are launch-off-shift and broadside. In the launch-off-shift technique, the last shift of the scan chain load also serves as the launch event. This last shift and the capture are skewed close together to produce an at-speed launch-to-capture clock frequency. Launch-off-shift has the advantage of only needing an ATPG tool to create combinatorial test vectors that are quick and easy to create. But the scan chains are shifted at-speed that may contribute to yield loss.
In the broadside approach, the entire scan chain is shifted at slow speed and then a pair of at-speed pulses are used for launch and capture. The results can then be shifted out at slow speed. Thus, broadside does not require the scan chains to shift at-speed, as in launch-off-shift. However, the ATPG pattern must be sequential, which increases the test pattern generation time and may result in higher pattern count. Sequential patterns are more complicated than combinatorial because the ATPG tool has to plan one cycle ahead to account for the fact that data captured in the first cycle is overwritten by data captured in the second cycle.
As integrated circuits becoming smaller and faster, current at-speed testing techniques may fail to detect circuit defects. A failure to detect such defects increases the defects per million (DPM) of a processor. Too many undetected time-based defects directly impacts the quality of products delivered to customers.